The reason I want to use timers for the step pulse is to free up the mega for other tasks in between speed ramps and counting steps (hierarchical state machine).īased on my "simple sketch" trials (prior to writing the CL42T class), I concluded that I can set up the timers and an OCR array for the desired movement, start the movement, and then simply monitor for the end of the domino line via one of two stop conditions: The dual motor subassemblies are strategically placed on the same timer as the motors need to be synchronized while running, and I can toggle both output compare pins on a single timer at the same frequency, given the appropriate bits are set in the TCCRA register. The final application will have a total of seven stepper drives, using the following timer outputs: In this application, each stepper motor has it's own dedicated timer output pin. The OCnx behaviors for CTC mode are detailed in table 17-3 on page 155 of the datasheet. Furthermore, in "Compare Output Mode, non-PWM", the output compare pins (in my particular test case, OC3A) can be toggled on compare match by setting the appropriate COMnx bits in the TCCRA register. "CTC" is the "clear timer on compare match" mode (table 17-2 on page 145, and section 17.9.2 starting on page 145), wherein the timer/counter increments until TCNT matches OCR or ICR, sets an output compare match flag (and calls the associated interrupt if enabled in TIMSK), then resets TCNT from zero. More specifically, Chapter 17, section 9, explains the modes of the timers. The way I understand the information in the datasheet, the OCR and ICR registers can be manipulated via interrupts, and (EDIT: bold) placing the timer in CTC output toggle mode will cause changes to the OCR or ICR value to affect the frequency of the rising edge of the pulses. How do you intend to let multiple steppers run at different step rates?Īgreed - it is explained in great detail in the datasheet.
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